Nexperia NXU0x04 Voltage-Level Translating Buffers
Nexperia NXU0x04 Voltage-Level Translating Buffers are 4-bit, dual-supply level translating buffers with 3-state outputs. These buffers feature four data inputs, four data outputs, and an output enable input. VCCA and VCCB can be supplied at any voltage between 0.9V and 5.5V, making the devices suitable for translating between any voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and 5.0V). The Nexperia NXU0x04 devices facilitate asynchronous communication between data buses. These buffers transmit data in a fixed direction (unidirectionally) from the A bus to the B bus on four channels. The OE pin can be referenced to the VCCA and VCCB domains, and when the OE pin is set to LOW, the output is disabled and enters a high-impedance OFF state, which isolates the buses. The OE pin can be left floating or externally pulled down to the ground to ensure the high-impedance state of the output during power up/down.
These Nexperia devices ensure low static and dynamic power consumption across the entire supply range and are fully specified for partial power-down applications using IOFF. The IOFF circuitry prevents damaging backflow currents through the device when powered down or if one of the power supplies is disconnected (floating). No power supply sequencing is required, and output glitches during power supply transitions are prevented. As a result, glitches will not appear on the output for supply transitions during power-up/down.
Features
- AEC-Q100 (Grade 1) qualified (-Q100x components)
- Supports
- NXU0104 for GPIO interfaces
- NXU0204 for 4-wire UART interfaces
- NXU0304 for SPI interfaces
- Wide 0.9V to 5.5V supply voltage range (VCCA or VCCB)
- Low power consumption for 1.1V to 5.5V supply voltage range
- 3µA (Tamb = +25°C)
- 5µA (Tamb = -40°C to +125°C)
- Schmitt-trigger inputs with integrated static high ohmic pull-down resistor on the input
- 250Mbps maximum data rate (≥1.8V to 5V translation)
- Output enable (OE) allows connection to VCCA or VCCB domain
- Suspend mode when either one of the supply voltages is below 100mV or disconnected (floating)
- Low noise overshoot and undershoot <10% of VCCO
- IOFF circuitry provides partial power-down mode operation
- Latch-up performance exceeds 100mA per JESD78D Class II
- Specified from -40°C to +85°C and -40°C to +125°C
- Complies with JEDEC standard
- JESD8-12 (0.9V to 1.3V)
- JESD8-11 (1.4V to 1.6V)
- JESD8-7 (1.65V to 1.95V)
- JESD8-5 (2.3V to 2.7V)
- JESD8C (2.7V to 3.6V)
- JESD12-6 (4.5V to 5.5V)
- ESD protection
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2500V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1500V
- Package options
- DHVQFN-14 with side-wettable flanks enabling Automated Optical Inspection (AOI) of solder joints, 2.5mm × 3mm × 0.85mm
- DHXQFN-14, 2mm × 2mm × 0.48mm, 0.4mm pitch
- TSSOP-14, 4.4mm width
- XQFN-12, 1.70mm × 2.0mm × 0.50mm
Applications
- General purpose I/O level translation
- Supports push-pull voltage translation as UART, SPI, and JTAG protocols
- Noisy environments or slow input signals
- Consumer
Schematics
NXU0104 Typical GPIO Application
NXU0204 Typical 4-Wire UART Application
NXU0304 Typical SPI Interface Application
Development Boards
Nexperia Placas de Avaliação NEVB-NXU0x04UL
PCBs containing the NXU0x04 Dual-Supply Voltage-Level Translating Buffers.
Publicado: 2024-10-17
| Atualizado: 2025-08-06