Analog Devices Inc. AD9545 Clock Synchronizers & Translators

Analog Devices Inc. AD9545 IEEE1588 Version 2 1pps Synchronizers and Adaptive Clock Translators support existing and emerging ITU standards for the phase, frequency, and time of day over service provider packet networks. The AD9545 devices offer high-precision, multi-output clock generator functions, and with two on-chip jitter cleaning digital PLL cores. 

Analog Devices AD9545's 10 clock outputs can be synchronized to any one of up to four input references. The device's digital phase-locked loops (PLLs) minimize the timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.


  • Dual DPLL synchronizes 1Hz to 500MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references
  • Complies with ITU-T G.8262 and Telcordia GR-253
  • Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, G.825, and G.8273.2
  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50ppb
  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
  • Programmable digital loop filter bandwidth: 10-4 to 1850Hz
  • Two independent, programmable auxiliary NCOs (1Hz to 65,535Hz, resolution < 1.4 × 10−12Hz), suitable for IEEE-1588 Version 2 servo feedback in PTP applications
  • Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
  • Programmable priority-based reference switching with manual, automatic revertive, and automatic non-revertive modes supported
  • 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as two single-ended outputs (1Hz to 500MHz)
  • 2 differential or four single-ended input references Cross point mux interconnects reference inputs to PLLs
  • Supports embedded (modulated) input/output clock signals
  • Fast DPLL locking modes
  • Supports a 25MHz to 52MHz crystal resonator, TCXO, or OCXO for system clock and provides for system clock frequency stability compensation
  • External EEPROM support for autonomous initialization
  • Single 1.8V power supply operation with internal regulation
  • Built-in temperature monitor/alarm and temperature compensation for enhanced zero delay performance


  • GPS, PTP (IEEE-1588), and SyncE jitter cleanup and synchronization
  • Optical transport networks (OTN), SDH, and macro and small cell base stations
  • OTN mapping/demapping with jitter cleaning
  • Small base station clocking, including baseband and radio
  • Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
  • Cable infrastructures
  • Carrier Ethernet

Functional Block Diagram

Analog Devices Inc. AD9545 Clock Synchronizers & Translators

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Publicado: 2017-10-31 | Atualizado: 2022-10-27