
Analog Devices Inc. AD9234 12-Bit Dual ADC
Analog Devices Inc. AD9234 12-Bit Dual Analog-to-Digital Converters are dual, 1GSPS ADCs optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. AD9234's on-chip buffer and sample-and-hold circuit are specifically designed for low power, small size, and ease-of-use in sampling wide bandwidth analog signals. This design is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC includes wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate-by-2 block.Features
- JESD204B (Subclass 1) coded serial digital outputs
- 1.5W total power per channel at 1GSPS (default settings)
- SFDR = 79dBFS at 340MHz
- SNR = 63.4dBFS at 340MHz (AIN = −1.0dBFS)
- ENOB = 10.4 bits at 10MHz
- DNL = ±0.16LSB
- INL = ±0.35LSB
- Noise density = −151dBFS/Hz at 1GSPS
- 1.25V, 2.5V, and 3.3V dc supply operation
- Flexible termination impedance
- 400Ω, 200Ω, 100Ω, and 50Ω differential
- No missing codes
- Internal ADC voltage reference
- 2GHz usable analog input full power bandwidth
- 95dB channel isolation/crosstalk
- Amplitude detect bits for efficient AGC implementation
- Differential clock input
- Optional decimate-by-2 DDC per channel
- Differential clock input
- Integer clock divide by 1, 2, 4, or 8
- Flexible JESD204B lane configurations
- Small signal dither
Applications
- Communications
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- Point-to-point radio systems
- Digital predistortion observation path
- General-purpose software radios
- Ultrawideband satellite receiver
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- Digital oscilloscopes
- High speed data acquisition systems
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Functional Block Diagram

Publicado: 2014-10-06
| Atualizado: 2022-03-11